1. Field of the Invention
Embodiments of the present invention relate generally to image sensors and methods and, in specific embodiments, to image sensors with column readout circuits.
2. Related Art
Image sensors have found wide application in consumer and industrial electronics, and have enabled an explosion in a number of digital cameras and digital video devices used for work and entertainment. In many applications, and especially in industrial applications, there is a constant demand for image sensors with faster processing speed and better image quality. Thus, it is advantageous to develop new circuits and techniques that allow for improved performance of image sensors.
FIG. 1 illustrates an architecture of a related art image sensor 1. As illustrated in FIG. 1, the image sensor 1 comprises a pixel array 8, a row driver 29, an analog-to-digital conversion (ADC) controller 85 and a plurality of column readout circuits 86. The pixel array 8 comprises pixels 2 that are arranged in rows and columns. Each pixel 2 comprises a light sensitive element, such as a photodiode, or the like, to sample light intensity of a corresponding portion of a scene being imaged, and each pixel 2 is configured to produce an analog pixel signal based on the sampled light intensity. The row driver 29 supplies control signals to the pixels 2 in the pixel array 8 to control an operation of the pixels 2.
Pixels 2 that are in a same row of the pixel array 8 share common row control signals from the row driver 29. For example, pixels 2 in a first row of the pixel array 8 share common row control lines 211 for receiving control signals from the row driver 29. Similarly, pixels 2 in a second row of the pixel array 8 share common row control lines 212 for receiving control signals from the row driver 29, and pixels 2 in an hth row of the pixel array 8 share common row control lines 21h for receiving control signals from the row driver 29. Pixels 2 that are in a same column of the pixel array 8 may share a common column readout line to provide output. For example, pixels 2 in a first column of the pixel array 8 share a column readout line 221, pixels 2 in a second column of the pixel array 8 share a column readout line 222, and pixels 2 in an mth column of the pixel array 8 share a column readout line 22m. The row driver 29 controls the pixels 2 to provide output row by row.
Further examples of related art image sensors are disclosed in the following references:    (i) U.S. Pat. No. 6,870,565 entitled “Semiconductor Imaging Sensor Array Devices with Dual-Port Digital Readout”, the entire contents of which are incorporated by reference herein;    (ii) U.S. Patent App. Pub. No. 2003/0043089 entitled “Doubling of Speed in CMOS Sensor with Column-Parallel ADCs”, the entire contents of which are incorporated by reference herein; and    (iii) A. Krymski et al., “A High Speed, 500 Frames/s, 1024×1024 CMOS Active Pixel Sensor”, 1999 Symposium on VLSI Circuits Digest of Technical Papers, 1999, Kyoto, Japan, pp. 137-138, the entire contents of which are incorporated by reference herein.
FIG. 2 illustrates an example of a design of the pixel 2. The pixel 2 in FIG. 2 is typically called a four transistor (4T) pixel. The pixel 2 includes a photodiode 11, a transfer transistor 112, a sense node 13, a reset transistor 114, a source follower transistor 116, and a row select transistor 118. The transfer transistor 112, the reset transistor 114, the source follower transistor 116, and the row select transistor 118 may each comprise, for example, an n-channel metal-oxide semiconductor field effect transistor (NMOS transistor), or the like.
The pixel 2 illustrated in FIG. 2 is provided as an example of a pixel in an nth row and a jth column of a pixel array, such as the pixel array 8 (refer to FIG. 1), and the pixel 2 receives a transfer signal (tx) over a transfer signal line 21n1, a reset signal (rst) over a reset signal line 21n2, and a row select signal (rowsel) over a row select signal line 21n3. The transfer signal line 21n1, the reset signal line 21n2, and the row select signal line 21n3 are shared by all pixels in an nth row of a pixel array, such as the pixel array 8 (refer to FIG. 1), and the transfer signal (tx), the reset signal (rst), and the row select signal (rowsel) are provided from a row driver, such as the row driver 29 (refer to FIG. 1). The pixel 2 in FIG. 2 provides output to a column readout line 22j.
As illustrated in FIG. 2, the photodiode 11 is a buried type photodiode with a substrate serving as an anode and an n− plate of the photodiode 11 is connected to a source of the transfer transistor 112. A gate 12 of the transfer transistor 112 is connected to the transfer signal line 21n1, and the gate 12 of the transfer transistor 112 may also be called the transfer gate 12. A drain of the transfer transistor 112 is connected to the sense node 13. A source of the reset transistor 114 is connected to the sense node 13, and a drain of the reset transistor 114 is connected to a supply voltage (Vdd) provided from a power supply (not shown). A gate 14 of the reset transistor 114 is connected to the reset signal line 21n2, and the gate 14 of the reset transistor 114 may also be called the reset gate 14.
A drain of the source follower transistor 116 is connected to the supply voltage (Vdd) provided from the power supply (not shown), and a source of the source follower transistor 116 is connected to a drain of the row select transistor 118. A gate 16 of the source follower transistor 116 is connected to the sense node 13. A source 19 of the row select transistor 118 is connected to the column readout line 22j, and the source 19 of the row select transistor 118 may also be called the pixel output area 19. The pixel output area 19 provides a pixel output (pout) signal to the column readout line 22j. A gate 18 of the row select transistor 118 is connected to the row select signal line 21n3.
With reference again to FIG. 1, each column readout circuit 86 is connected to receive analog signals from a corresponding column readout line, and is configured to provide digital output on a corresponding output line. For example, the column readout circuit 86 for the first column is connected to the column readout line 221 for receiving input, and is connected to an output line 821 for providing output. Similarly, the column readout circuit 86 for the second column is connected to the column readout line 222 for receiving input, and is connected to an output line 822 for providing output, and the column readout circuit 86 for the mth column is connected to the column readout line 22m for receiving input, and is connected to an output line 82m for providing output. The ADC controller 85 is configured to provide control signals to the plurality of column readout circuits 86 over one or more control lines 83.
FIG. 3 illustrates a portion of the related art image sensor 1 (refer to FIG. 1) with circuitry for performing readout from a jth column of the pixel array 8 (refer to FIG. 1). As illustrated in FIG. 3, the column readout circuit 86 for the jth column is connected to receive pixel output (pout) signals over the column readout line 22j, and is connected to receive control signals from the ADC controller 85 (refer to FIG. 1) including: (1) an amplifier reset (amprst) signal over a control line 831; (2) an ADC autozero signal (ADC autozero) over a control line 832; (3) a sample and hold signal (S/H into ADC) over a control line 833; and (4) an ADC conversion signal (ADC conversion) over a control line 834. The column readout circuit 86 provides output over an output line 82j.
The column readout circuit 86 includes a current sink transistor 91, a capacitor 92, a feedback capacitor 93, a switch 94, an amplifier 95, and a column ADC circuit 96. A first terminal of the current sink transistor 91 is connected to the column readout line 22j, and a second terminal of the current sink transistor 91 is connected to a fixed voltage, such as ground or another suitable voltage. A gate of the current sink transistor 91 is connected to a voltage V1n. A first terminal of the capacitor 92 is connected to the column readout line 22j, and a second terminal of the capacitor 92 is connected to a negative input of the amplifier 95. A first terminal of the feedback capacitor 93 is connected to the negative input of the amplifier 95, and a second terminal of the feedback capacitor 93 is connected to an output of the amplifier 95. A first terminal of the switch 94 is connected to the negative input of the amplifier 95, and a second terminal of the switch 94 is connected to an output of the amplifier 95. The switch 94 is controlled by the amplifier reset (amprst) signal provided on the control line 831.
The output of the amplifier 95 is connected to the column ADC circuit 96. The column ADC circuit 96 is also connected to the control lines 832, 833, and 834, for receiving the ADC autozero signal, the S/H into ADC signal, and the ADC conversion signal, respectively. The column ADC circuit 96 is configured to perform an autozero operation in accordance with the ADC autozero signal. The column ADC circuit 96 is configured to sample and hold an output from the amplifier 95 in accordance with the S/H into ADC signal. The column ADC circuit 96 is configured to perform analog-to-digital conversion of an analog signal in accordance with the ADC conversion signal and to provide the digital result as output on the output line 82j.
FIG. 4A illustrates a signal timing chart for a related art pixel readout scheme. With reference to FIGS. 1, 2, 3, and 4A, the related art pixel readout scheme proceeds as follows during a row (line) time for a row n:
(a) the row driver 29 provides a HIGH signal for rst on the reset signal line 21n2 to reset the sense node 13 of each pixel 2 in the row n, the ADC controller 85 provides a HIGH signal for amprst on the control line 831 to reset the amplifier 95 of each column readout circuit 86, and the ADC controller 85 provides a HIGH signal for ADC autozero on the control line 832 to cause the column ADC circuit 96 of each column readout circuit 86 to perform an autozero function;
(b) the row driver 29 provides a HIGH signal for tx on the transfer signal line 21n1 to start a charge transfer process from the photodiode 11 to the sense node 13 in each pixel 2 in the row n;
(c) the ADC controller 85 provides a HIGH signal for S/H into ADC on the control line 833, at which time a signal value for each pixel in the row n can be provided over the corresponding column readout line to the corresponding column readout circuit 86, such that a difference between the signal value and the stored reset value is amplified by the amplifier 95 and sampled and held by the column ADC circuit 96; and
(d) the ADC controller 85 provides a HIGH signal for ADC conversion on the control line 834 to cause the column ADC circuit 96 of each of the column readout circuits 86 to perform analog-to-digital conversion of the sampled and held value.
As illustrated in FIG. 4A, once the pixel readout scheme has completed readout for a row n, the readout starts for a next row (n+1), and the readout scheme is repeated during that next row (line) time for the row (n+1). The readout continues in that fashion, row-by-row, for all rows in the pixel array 8 (refer to FIG. 1).
FIG. 4B provides a generalized description of a related art column readout scheme. With reference to FIGS. 1, 3, and 4B, in various complimentary metal oxide semiconductor (CMOS) image sensor readout schemes, a photo-signal from a pixel, such as each of the pixels 2, is represented with two voltage signals that are read out with one following another from the pixel. For simplicity, the two pixel signals output from the pixel can be called “sig1” and “sig2.” One of the pixel signals (either sig1 or sig2) from a pixel represents a value of an empty sense node or readout node in the pixel after the pixel has been reset, and the other of the pixel signals (the other of sig1 or sig2) represents a value of the same sense node as filled with photo-charge from an exposure. The order of whether the reset signal is read out first (as sig1) or second (as sig2) depends on the details of the pixel implementation.
At the beginning of a first row time (denoted as “Row 1” in FIG. 4B) a sig1 is read out from each pixel, such as the pixels 2, in a first row of a pixel array. Also, an amplifier in each column readout circuit, such as the amplifier 95, is reset (denoted “amprst” in FIG. 4B), and a column ADC circuit in each column readout circuit, such as the column ADC circuit 96, is autozeroed (denoted “ADC AZ” in FIG. 4B). Then, a sig2 is read out from each pixel, such as the pixels 2, in the first row of the pixel array. A difference between the signals sig1 and sig2 is amplified (denoted “amp” in FIG. 4B) by the corresponding amplifier, such as the amplifier 95, in each column readout circuit, and the amplified difference of the signals is sampled and held (denoted “ADC SH” in FIG. 4B) by the corresponding column ADC circuit, such as the column ADC circuit 96, in each column readout circuit. During the remaining time of the first row time, the amplified and sampled and held difference of sig1 and sig2 is converted from analog to a digital value (denoted “ADC conv” in FIG. 4B) by the corresponding column ADC circuit, such as the column ADC circuit 96, in each column readout circuit.
Once the analog to digital conversion is complete for signals from the first row, the first row time ends, and then a second row time (denoted “Row 2” in FIG. 4B) begins. During the second row time, similar operations are performed as were performed during the first row time, but the signals sig1 and sig2 are obtained from pixels in a second row of the pixel array rather than the first row. Once the analog to digital conversion is complete for signals from the second row, the second row time ends, and then a third row time (denoted “Row 3” in FIG. 4B) begins. During the third row time, similar operations are performed as were performed during the first row time, but the signals sig1 and sig2 are obtained from pixels in a third row of the pixel array rather than the first row. The process then continues for each row in the pixel array.
In the readout scheme of FIG. 4A and the readout scheme of FIG. 4B, approximately one-half of the row (line) time is available for pixel operations, and the other half of the row time is devoted to analog-to-digital conversion. During the row operations, time is needed for the pixel operations, such as pixel reset and pixel charge transfer, and time is also needed for settling of the pixel, the column readout line, and the amplifier after completing the pixel operation. As a result, in the readout schemes of FIG. 4A and FIG. 4B, the time allocated to a particular row operation (such as pixel reset or pixel charge transfer) may be insufficient to fully complete that particular row operation. This may cause image non-uniformities and excessive noise from incomplete correlated double sampling (CDS). Such problems become worse in high speed image sensors with limited row times.